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SolStice Engineering is very fortunate to have one of the world's foremost signal integrity engineers, Robert Cutler, as a
member of our team. Robert has been consulting in the field of interconnection technology since 1984. This has included
electrical design, packaging, and production. The primary focus of his work is simulation and analyses of high-speed
interconnect. This involves both the board and backplane level.
Achieving required performance goals within the constraints of real designs (limited board real estate, parts placement for
thermo control, PWB producibility, etc.) is the key to a successful system. The first article must perform in order to meet critical
time-to-market requirements. CAD layout rules are developed based on simulation results and the CAD layout process works
hand-in-hand with this analysis. It is critical to ensure that design rules are implemented properly and that performance vs.
routeability tradeoffs can be made in real time with minimal schedule impact.
As part of his work, Robert was instrumental in the development of the CompactPCI specification that was accepted by the
PICMG as of 12/1/95. A unique termination scheme was developed that effectively damps the bus without adversely impacting
bus speed. GigE, KR, PCIeG2, XAUI, and serial channels up to 12+Gbps are among the technologies that he is simulating and
helping to implement in telecom and networking systems. This work involves modeling passive channels in the frequency
domain using various board substrates (FR406, Nelco 4000-13/13SI, Megtron 6, etc.) and connector systems to help tradeoff
performance vs. cost for the specific design. 3D modeling of via and launch structures is performed using Ansoft HFSS, a 3D
field solver. Robert’s work includes simulating DDR2 & DDR3 interfaces using both modules and stand alone SDRAM chips.
Robert holds a B.S. in Electrical Engineering from Carnegie-Mellon University. Published articles include:
Reducing Development Time in High Performance Computing Systems for the High Performance Computing Symposium
in 1995.
Simulating Hot Swap in CompactPCI in January 1999 issue of Computer Design.
Reducing Chassis System Costs Without Sacrificing Performance and Bandwidth in the October 2003 EE Times Net Seminar
series.
A partial list of signal integrity analysis clients includes:
member of our team. Robert has been consulting in the field of interconnection technology since 1984. This has included
electrical design, packaging, and production. The primary focus of his work is simulation and analyses of high-speed
interconnect. This involves both the board and backplane level.
Achieving required performance goals within the constraints of real designs (limited board real estate, parts placement for
thermo control, PWB producibility, etc.) is the key to a successful system. The first article must perform in order to meet critical
time-to-market requirements. CAD layout rules are developed based on simulation results and the CAD layout process works
hand-in-hand with this analysis. It is critical to ensure that design rules are implemented properly and that performance vs.
routeability tradeoffs can be made in real time with minimal schedule impact.
As part of his work, Robert was instrumental in the development of the CompactPCI specification that was accepted by the
PICMG as of 12/1/95. A unique termination scheme was developed that effectively damps the bus without adversely impacting
bus speed. GigE, KR, PCIeG2, XAUI, and serial channels up to 12+Gbps are among the technologies that he is simulating and
helping to implement in telecom and networking systems. This work involves modeling passive channels in the frequency
domain using various board substrates (FR406, Nelco 4000-13/13SI, Megtron 6, etc.) and connector systems to help tradeoff
performance vs. cost for the specific design. 3D modeling of via and launch structures is performed using Ansoft HFSS, a 3D
field solver. Robert’s work includes simulating DDR2 & DDR3 interfaces using both modules and stand alone SDRAM chips.
Robert holds a B.S. in Electrical Engineering from Carnegie-Mellon University. Published articles include:
Reducing Development Time in High Performance Computing Systems for the High Performance Computing Symposium
in 1995.
Simulating Hot Swap in CompactPCI in January 1999 issue of Computer Design.
Reducing Chassis System Costs Without Sacrificing Performance and Bandwidth in the October 2003 EE Times Net Seminar
series.
A partial list of signal integrity analysis clients includes:
- Alcatel-Lucent
- Amphenol
- Boeing
- Ciena
- Cisco
- Ericsson
- Extreme Networks
- General Dynamics
- IBM
- Intel
- LSI Logic
- McAfee
- Motorola
- Nokia
- Nortel
- PICMG
- Qualcomm
- Raytheon
- Spirent
- Sun Microsystems
- Tellabs
- VITA
- Vitesse
| If you need help with signal integrity or PCB layout issues, please call or email us and we'll be happy to help. |
| Signal Integrity Analysis & PCB Design Guideline Creation |